Author : Vasantha Kumar B.V.P, Dr. N. S. Murthy Sharma, Dr. K. Lal Kishore and Jibanjeet Mishra
Affiliation : Synopsys (India) Pvt. Ltd
Country : India
Category : Digital Signal & Image Processing
Volume, Issue, Month, Year : 2, 4, December, 2011
In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.
Post a Comment