Affiliation : Hosei University
Country : Japan
Category : Computer Science & Information Technology
Volume, Issue, Month, Year : 8, 9, June, 2018
SysML activity diagrams are often used as models for software systems and its correctness is likely to significantly affect the reliability of the implementation. However, how to effectively verify the correctness of SysML diagrams still remains a challenge. In this paper, we propose a testing-based formal verification (TBFV) approach to the verification of SysML diagrams, called TBFV-M, by creatively applying the existing TBFV approach for code verification. We describe the principle of TBFV-M and present a case study to demonstrate its feasibility and usability. Finally, we conclude the paper and point out future research directions.
Keyword : SysML activity diagrams, TBFV, test path generation, formal verification of SysML diagram
For More Details : https://airccj.org/CSCP/vol8/csit88904.pdf
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