Author : Shelja A S
Affiliation :
Department of Electronics and Communication Engineering, NCERC
Country : India
Category : Computer Science & Information Technology
Volume, Issue,
Month, Year
: 6, 9, November, 2016
Abstract
An
implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG
is an established technology and industry standard for on-chip boundary scan
testing of SoCs. JTAG TAP controllers are becoming a delivery and control
mechanism for Design For Test. The objective of this work is to design and
implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of
the standard. The test logic architecture also includes the Test Mode
Persistence controller and its associated logic. This work is expected to serve
as a ready to use module that can be directly inserted in to a new digital IC
designs with little modifications.
Keyword : IP core; IEEE 1149.1, TAP; TMP controller; JTAG;
boundary scan; DFT
For More Details : https://airccj.org/CSCP/vol6/csit65610.pdf
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