Volume, Issue, Month, Year : Vol 7 , No 5/6, December, 2016
ABSTRACT
This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis
and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR
digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in
term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing
area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.
No comments:
Post a Comment