Author : Bolla Leela Naresh, N.V.Narayana Rao and Addanki Purna Ramesh
Affiliation : Sri Vasavi Engg College
Country : India
Category : Digital Signal & Image Processing
Volume, Issue, Month, Year : 2, 4, December, 2011
This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended.
Keyword : Deblocking filter, SOC, NIOS-II soft processor, FPGA
For More Details:https://allconferencecfpalerts.com/cfp/view-paper.php?eno=5210