Wednesday, October 13, 2021

Arithmetic Operations in Multi-Valued Logic


Author :  Vasundara Patel K. S and K. S Gurumurthy

Affiliation :  Vishweshwaraiah Technological University

Country :  India

Category :  Computer science&Information Technology

Volume, Issue, Month, Year :  1, 1, March, 2010

Abstract :

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

Keyword :  Multiple-valued logic, Quaternary logic, Modulo-n addition and multiplication, Galois addition and multiplication.

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